1. Field of the Invention
The present invention relates to a semiconductor memory device having a test pattern generating circuit. Particularly, the present invention relates to a semiconductor memory device having a test pattern generating circuit for carrying out "burn-in", which is a test of the memory devices carried out before final acceptance, as described below.
2. Description of the Related Art
In the manufacturing process of the semiconductor memory devices, many kinds of tests are carried out before the memory devices are finally accepted, in order to discover defective memory devices before that acceptance, and the aging process usually called "burn-in" is carried out as one of the above tests. The above burn-in test is carried out at a certain stage of the following process, that is, assembling, pre-burn-in test, burn-in test (aging), and post-burn-in test (final test). In the above burn-in test, predetermined clock signals (timing signals) such as row and column address strobe signals in an address multiplexed dynamic random-access memory (RAM), address signals, a write enable signal, and write-in data are input to a memory circuit under a high temperature and a high power supply voltage and a check is made of whether or not an obstacle is generated in a certain memory device, which device usually includes a defective memory circuit, a defective memory cell, a defective bonding wire, etc, and only has a short life time.
In this case, the temperature is kept within a range of, for example, 70.degree. to 125.degree. C., and the power supply voltage is set to a value, for example, higher than 6 volts when the standard value of that voltage is 5 volts.+-.10%.
As above-mentioned, the burn-in test is carried out under high temperature and high voltage conditions, and this burn-in test corresponds to a so-called acceleration test.
As a result, an IC chip that will generate a certain obstacle when used in a usual mode must generate such an obstacle (insulation destruction of gate oxide film or electromigration of connection, etc.) when the above burn-in test is carried out. Therefore, IC chips which have generated such an obstacle during the burn-in test are detected by the above final test, which is carried out after the above burn-in test, and these IC chips are removed as the defective products, and thus are prevented from being placed on the market. Thus, an improvement of the reliability of the products is ensured.
At present, as mentioned above, the above burn-in test is carried out for almost all of the semiconductor memory chips before final acceptance, in order to improve the reliability of the products. The burn-in test is carried out by a dynamic operation, and clock signals (row and column address strobe signals), address signals, a write enable signal, and write-in data are supplied from an external input to each of the IC chips (memory chips) in accordance with a predetermined test pattern.
In the prior art, however, as the above signals and the write-in data are supplied to each of the IC chips from a driver circuit provided in an external apparatus for carrying out the burn-in test through connectors provided on the burn-in board, it is impossible to prevent a disturbance by a drive waveform, such as overshoot or undershoot. As a result, the memory circuit provided on each of the IC chips often cannot perform a normal operation, and in the case of a CMOS memory device, when a predetermined negative voltage is generated due to the above undershoot, a thyristor formed by PNPN construction in the memory circuit often turns ON (causes so-called latch-up), and as a result, some of elements in the memory circuit are destroyed. Also, in the prior art, it is necessary to arrange a lot of wiring on the burn-in board and to provide many contact segments in the connectors, and as a result, the construction of the apparatus for carrying out the burn-in test is complicated and the size of the above apparatus is too large.